Mr. 3D IC—aka Herb Reiter—spoke to an attentive group of packaging experts about the state of 3D IC technical and business development today at a MEPTEC luncheon held at the “luxurious” Biltmore Hotel in cental Silicon Valley. I’ve written about Reiter before but I’ve just found out at lunch that he’s been crowned as the “King of 3D ICs” by Françoise von Trapp, Editorial Director of 3D-ICs.com and the Queen of 3D (as proclaimed at SEMICON Europa 2007), because of the four years Reiter has put into learning about, cheering on, and supporting the growth of 3D IC assembly. (I am pretty certain that Reiter is glad he’s not been named the Queen of 3D.)
Reiter held the lunch crowd for more than an hour with a blisteringly fast overview of the business and technology of 3D IC packaging. Here are some of the most important points he made during his talk:
Stop thinking about 3D packaging technology as “3D IC” technology and start thinking of it as “3D systems” technology. There are two primary reasons for this advice. First, there are many IC process technologies that do not mix on one chip for technical or for economic reasons. From a technical perspective, logic, memory, and analog processes are sufficiently different in terms of metal layers and device geometry that forcing the three to meld on one die creates severe engineering compromises, which detract from overall performance.
From an economic perspective, forced mating of logic, memory, and analog functions on one silicon die will actually increase the cost of these functions. That might be counterintuitive given our decades-long quest for monolithic design but memory and analog costs suffer from occupying space on die designed with 10 or more metal layers to accommodate high-density logic routing. Logic costs suffer from the huge increase in die size needed to accommodate vast memory acreage or the relatively large device footprints of analog components—even passives such as capacitors. For example, imagine chewing up large amounts of expensive 28nm or 20nm silicon to lay down capacitors in a switched filter. Costs increase from acreage growth and from yield declines as chips get bigger.
Here’s one of Reiter’s slides with a compelling cost analysis of 3D stacking done by Associate Professor Yuan Xie at Pennsylvania State University:
The two left-hand graphs show that partitioning 300mm2 chips, stacking them, and bonding them as a 3D stack reduces manufacturing costs by 25% for die with 32nm minimum feature sizes and a whopping 46% (nearly half!) for die with 22nm minimum feature sizes. The two right-hand graphs show that the savings are larger still for bigger die (500mm2).
(For more information, see Yuan Xie’s paper “System-Level Cost Analysis and Design Exploration for Three-Dimensional Integrated Circuits (3D ICs)”)
At the same time, said Reiter, you must remember that 3D IC stacking and assembly is not a manufacturing panacea—just like everything else in the electronics industry. There’s no magic technology that solves every technical and economic problem when sprinkled liberally on a design project. Sorry.
Another interesting remark from Reiter is that he’s far more worried about the business side of the 3D IC equation. He said, and I agree, that there are plenty of smart people to solve the technical problems. 3D IC designs are being done now. Xilinx is shipping Virtex-7 2000T FPGAs “in volume” now. Last week, the TSMC CoWoS test vehicle appeared in the Cadence booth at DAC. (See “3D Thursday: Want to see a closeup of the TSMC 3D IC test vehicle?”) It’s the business problems that will prove tough, said Reiter, who then compared this situation to the one we in the industry experienced in the late 1990s and early 2000s as the IC industry transitioned from a field of vertically integrated IDMs to a largely fabless business model. “Even IBM and Samsung cannot make [3D IC] technology cost effective on their own,” he said. The industry must build a collaborative ecosystem and the only way we can do that is to think in terms of reducing system cost, not just BOM cost.
Jumping back to the technical side, Reiter projected this slide from Dr. Paul Franzon of North Carolina State University:
Take a look at the longest bars representing operations that consume the most energy. The three operations that consume the most energy are DDR3 and LPDDR2 SDRAM transfers and SERDES I/O operations. These are all off-chip I/O operations. By no small coincidence, these are the operations that most benefit from 3D IC assembly because you can significantly reduce the size of I/O drivers (and their energy consumption) when driving chip-to-chip through TSVs (through-silicon vias).
(For more information, see “3D Technologies For Low Power Integrated Circuits”)
How much energy can you save? About 6x, according to this slide that Reiter took from a Cadence presentation at last week’s Design Automation Conference in San Francisco:
Where do these Cadence figures come from? Reiter explained that, to his knowledge, Cadence has done 8 or 9 complex, successful 3D designs with its partners so far. Note that 6x improvement in energy consumption is a big deal. Design teams will kill themselves for a 10% improvement and we’re talking 6x here.
Reiter then said that 3D IC packaging offers many benefits, which he amply illustrated during his talk, but that the technology isn’t right for every project. How do you decide if it’s right for a particular project? Reiter projected the best approach I’ve seen to making such a decision. He put up this prototype spider diagram:
As you can see, there are a lot of factors to consider. Some are technical: bandwidth, latency, and power dissipation. Many are economic: Form factor, NRE, time to market, unit cost and impact on system cost. Others are institutional: resources (internal and external), and risk elements. If you wanted a simple answer, sorry there isn’t one. If you wanted a real engineering problem to tackle, well there it is. Have at it.
One more slide that Reiter projected showed which types of system project might most benefit from 3D IC assembly:
The slide is from a few years ago and comes from Gartner. It suggests that products that are the most space and power constrained—media tablets, smartphones, and mobile PCs—stand to benefit most from 3D IC packaging and assembly. (I might easily add SSDs to this list because 3D memory stacking will make a huge difference in the amount of storage that vendors can stuff into industry-standard SSD form factors.)
Note: The “King” has spoken. Your audience has ended.
